Solder bump interconnections are used in flip-chip and other packaging technologies. The bump connections between the integrated circuit chip and substrate are historically referred to as Controlled-Collapse Chip Connections (C4). For many applications, power and ground bump interconnections are required to carry high currents, and these C4 interconnections are subject to electromigration or thermal failure.
For 100 μm diameter solder bumps placed on a pitch of 200 μm (commonly referred to as 4-on-8 bump arrays), a typical maximum current specification is 200 mA per bump, corresponding to an average current density through the bump of 2.3 kA/cm2. However, for practical designs of chip and substrate wiring, the current flow through the bump is not uniform, and peak current densities are much higher than the average density. This effect, known as current crowding, occurs due to the spreading resistance of different contact regions which constrict the current flow. This effect is illustrated in FIG. 1 and FIG. 2. There are many reports of studies concerning current crowding in C4 interconnections; a recent published review is K. N. Tu et al., J. Applied Physics 94 5451 (2003), and references contained therein.
The combination of peak current density exceeding about 10 kA/cm2, and chip temperatures in excess of 100° C., cause thermal and electromigration effects which eventually cause contact failure. The electromigration rate typically follows a Black's law relationship, where the failure rate increases roughly as the square of the peak current density. The failure mechanisms involve the formation of intermetallic compounds, particularly between the Sn solder component and various metallic components of the contact pad structure and wiring metal such as Cu or Al. As compared to the base solder material, the intermetallic compounds are brittle, and under thermal and electrical stress, tend to spall into the solder bump. Electromigration effects lead to formation of voids and cracks which eventually cause electrical failure of the contact.
For many applications, there is also a need to increase the bump array contact density to the chip, both for the purposes of increasing signal input-output capacity and also to improve control and performance of power distribution. Standard 4-on-8 bump arrays are being replaced with 3-on-6 designs, with 1-on-2 bump array technology under development. As the bump size decreases, the volume to surface area ratio decreases, suggesting that problems with intermetallic formation in small bumps will increase proportionately. Furthermore, unless the power supply and ground wiring is carefully scaled to match the bump density, there will be a tendency for average current density to increase for smaller bumps.
The strategies for formation of highly-reliable bump interconnections can be described in three categories. One strategy involves routing current to the interconnection through multiple wires from multiple directions in order to minimize the density of the current arriving at an interconnection to reduce the rate of electromigration in a bump structure. A second strategy utilizes barrier layer materials in contact with the solder. These barrier layer materials have an initial reaction with the solder during reflow to form certain stable intermetallic compounds, which further react slowly with the solder during subsequent thermal and electrical stress, to reduce the rate of electromigration failure. Yet another strategy involves increasing mechanical adhesion and integrity to extend the contact lifetime as electromigration effects proceed.
A common approach taken to improve interconnect electromigration lifetime is to route the current through multiple wires in order to spread the current as much as possible before the current reaches the interconnection and bump structure. For power or ground interconnections which must carry large currents, multiple wiring lines are connected to the bump contact pad as in FIGS. 8-11. To spread the current, the contact pad is made as large as possible, and the chip wiring is often connected to all four orthogonal sides of a contact pad. Wiring layout restrictions may limit the extent to which this approach can be implemented. Multiple pad contact lines can reduce current non-uniformities.
A straightforward method to improve the current uniformity in the interior of the pad, near the via edge of the bump-to-pad interface, is to increase the thickness of the top wiring level metal layer. If the thickness of the pad can be increased to approach the thickness of the bump, then the current distribution inside the bump will be nearly uniform. However, technological limitations of damascene processing for chip-side wiring generally restrict the maximum thickness of the top-level wiring to about 1 to 2 μm, far less than bump thicknesses which may span the range of about 10 μm to 100 μm. For typical organic or ceramic technology, the thickness of the wiring on the substrate side of the bump can be made moderately thick, about 20 μm. For small bumps with a diameter similar to the substrate wiring thickness, the current distribution on the substrate side of the bump will be relatively uniform. However, for bumps with a diameter much larger than the substrate wiring thickness, the current distribution will not be highly uniform on either the substrate site or the chip side of the bump. While thick substrate pad and wiring improves the distribution of current on the substrate side, in particular there remains a problem of current crowding on the chip side of the bump. The current is crowded near the edge of the bump, where contact pad metal intersects the bump.
One structure which increases the distance between the current crowded region and the solder is described by A. Yeoh et al., “Copper Die Bumps (First Level Interconnect) and low-K Dielectrics in 65-nm High Volume Manufacturing”, pp. 1611-1615, Electronic Components and Technology Conference, May 2006. In this structure, a thick Cu metal pillar replaces much of the solder bump; only a small solder region is present between the Cu pillar and substrate pad metal. Although the current is crowded at the intersection of the thin chip-side wiring and the Cu pillar, the current spreads out within the electrically conductive Cu pillar and becomes nearly uniform at the interface between the Cu pillar and solder metal. This Cu pillar technology is presently thought to have both advantages and disadvantages as compared to conventional C4 technology. A study of electromigration characteristics of Cu pillar structures has been described by J-W Nah et al., “Electromigration in Pb-free Solder Bumps with Cu Columns as Flip-Chip Joints”, pp. 657-662, Electronic Components and Technology Conference, May 2006.
A second strategy and common approach taken to improve bump contact reliability is to form layered pad metal structures with materials which have minimal chemical interaction with the C4 ball metal alloy, and form a barrier layer between the solder and wiring metal. The pad layer structure on the chip side of the bump has commonly been referred to as ball-limiting metallurgy (BLM) or under-bump-metallurgy (UBM). The pad layer structure on the substrate side is typically referred to as top-surface-metallurgy (TSM) or substrate pad surface finish. Typically, the BLM barrier layer pad materials contain refractory metals or near-refractory metals such as Ni, Cr, W or Ti. These barrier layer materials help suppress the formation of undesirable intermetallic compounds with the solder. Some form of barrier layer structure is needed to achieve good interconnect reliability, however, the most aggressive barrier layer structures utilized to date still do not guarantee very high interconnect reliability, particularly for Pb-free solder materials.
Typical solder bump materials may include a family of PbSn mixtures with different melting temperatures, spanning the range from eutectic PbSn, containing 37% Pb, up to “high-Pb” solder containing 95% Pb. Other solder materials are based on alloys containing metals such as In, Ag, Au, Zn, and Bi. For some time, there has been public concern about the use of Pb in electronic packaging, and there is a strong interest to incorporate “Pb-free” packaging solutions wherever possible. The Pb-free solder materials proposed to date are all based on the use of Sn as a major constituent, with minor components such as Cu and or Ag. There are many challenges to develop a robust interconnect contact technology based on Sn. Of these, it is known that the rate intermetallic formation increases with Sn composition in the solder.
A third general problem with C4 connections is physical adhesion, or mechanical bond strength. Metallic materials such as Cr or Ti are typically used to improve adhesion. These materials add manufacturing cost and can introduce additional complications. For example, Ti readily reacts with oxygen and hydrogen, creating compounds with high electrical resistivity, and which are subject to rapid chemical attack during processing. Since the electrical failure of bump contacts occurs concurrently with mechanical failure, improvement of mechanical adhesion is believed to increase contact reliability. New methods are needed to improve adhesion, without the introduction of additional metal materials.
A variety of structures and methods have been described to improve electromigration lifetime in Cu or Al wiring in chip back-end-of-line (BEOL) structures. It is known that the formation of grain boundaries perpendicular to current flow inhibits electromigration, called “bamboo” structures. Some of these approaches seek to inhibit electromigration through the construction of regions which do not allow grain boundaries form parallel to current flow, or suppress grain boundary formation altogether. Other approaches include the formation of refractory metal regions or plugs arranged in patterns with a periodicity smaller than the Blech length. For wire traces with sharp corners, Lur et al., U.S. Pat. No. 5,633,198, issued May 27, 1997, describes the use of parallel slots to spread out the current from the corner. However, the preferred embodiment shows a particular slot pattern which would not reduce current crowding.
One example of the suppression of flip-chip C4 electromigration failure is Mithal et al., U.S. Pat. No. 6,822,327 issued Jun. 20, 2000. Mithal describes a plurality of separate electrical “runner” wiring paths which supply current around the periphery of a bump.
Mistry et al., U.S. Pat. No. 6,077,726, issued Nov. 23, 2004. describes a means of reducing mechanical stress in C4 bumps through incorporation of a polyimide layer over the surface and edge of a passivation layer, within the contact pad region.
There are numerous examples of the use of various barrier layer materials in the bump contact pad region. One such example is Andricacos et al., U.S. Pat. No. 5,937,320 issued Aug. 10, 1999.